Port Switching using Switch Chip on RouterOS

Switch Chip features are implemented in RouterOS (complete set of features implemented starting from version v4.0).

Command line config is located under /interface ethernet switch menu.
This menu contains a list of all switch chips present in system, and some sub-menus as well.

/interface ethernet switch print
Flags: I - invalid
 #   NAME     TYPE         MIRROR-SOURCE   MIRROR-TARGET
 0   switch1  Atheros-8316 ether2          none

Port Switching
Switching feature allows wire speed traffic passing among a group of ports, like the ports were a regular Ethernet Switch (L2).
This feature can be configured by setting a master-port property to one ore more ports in /interface ethernet menu.
A master-port will be the port through which the RouterOS will communicate to all ports in the group.
Interfaces for which the master-port is specified become inactive – no traffic is received on them and no traffic can be sent out.

For example consider a router with five ethernet interfaces:

/interface ethernet print
Flags: X - disabled, R - running, S - slave
 #    NAME    MTU   MAC-ADDRESS       ARP      MASTER-PORT SWITCH
 0 R  ether1  1500  XX:XX:XX:XX:XX:AB enabled
 1    ether2  1500  XX:XX:XX:XX:XX:AC enabled  none        switch1
 2    ether3  1500  XX:XX:XX:XX:XX:AD enabled  none        switch1
 3    ether4  1500  XX:XX:XX:XX:XX:AE enabled  none        switch1
 4 R  ether5  1500  XX:XX:XX:XX:XX:AF enabled  none        switch1

Configuring a switch containing three ports: ether3, ether4 and ether5.
ether3 is now the master-port of the group.

/interface ethernet set ether4,ether5 master-port=ether3
 
/interface ethernet print
Flags: X - disabled, R - running, S - slave
 #    NAME    MTU   MAC-ADDRESS       ARP      MASTER-PORT SWITCH
 0 R  ether1  1500  XX:XX:XX:XX:XX:AB enabled
 1    ether2  1500  XX:XX:XX:XX:XX:AC enabled  none        switch1
 2 R  ether3  1500  XX:XX:XX:XX:XX:AD enabled  none        switch1
 3  S ether4  1500  XX:XX:XX:XX:XX:AE enabled  ether3      switch1
 4 RS ether5  1500  XX:XX:XX:XX:XX:AF enabled  ether3      switch1

Note: previously a link was detected only on ether5 (R Flag), as the ether3 becomes master-port the running flag is propagated to referring master-port.

 

 

A packet received by one of the ports always passes through the switch logic at first. Switch logic decides to which ports the packet should be going to. Passing packet up or giving it to RouterOS is also called sending it to switch chips CPU port.
That means that at the point switch forwards the packet to cpu port the packet starts to get processed by RouterOS as some interfaces incoming packet. While the packet does not have to go to cpu port it is handled entirely by switch logic and does not require any cpu cycles and happen at wire speed for any frame size.

 


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